Complex very large scale integrated circuit devices fabricated on a single semiconductor chip contain thousands of functional circuit elements which are inaccessible for discrete testing. Because of the complexity of the internal interconnections and their combinational interdependencies, testing for device integrity becomes increasingly time consuming as the number of circuit elements increases.
If by way of example a semiconductor chip were to have fifty input connections, the number of combinations of inputs is 2.sup.50. While one could apply that number of different input patterns, record the output responses, and compare those responses with the responses that ought to result, that is a herculean task and impossible for modern production testing.
A testing protocol as above-described, is described in the Giedd et al. U.S. Pat. No. 3,614,608 assigned to the assignee of the instant application. To reduce the number of patterns required for testing, Giedd et al. employed a random number generator to generate the test patterns. This expedient considerably reduces the number of patterns needed to test a device. This is true because a random pattern generator, unlike a binary counter, produces a succession of binary words wherein the split between binary zeros and ones approaches a 50% split for a substantial number of successive words, which number of words is considerably less than the total possible number of different words. Thus, each input to the device under test (DUT) has a 50% chance of receiving a binary zero or one input with a fewer number of input patterns.
A second expedient to reduce testing time is to employ weighted random patterns as inputs to the device under test (DUT). This ploy applies a statistically predetermined greater number of binary ones or binary zeros to the input pins of the DUT. The object is to apply a weighted test pattern that will have a maximum effect upon the inaccessible internal circuit elements.
A weighted random pattern test method is described by Carpenter et al. in U.S. Pat. No. 3,719,885 assigned to the assignee of the instant application. They employed a pseudo-random pattern generator to produce a random succession of binary words which were decoded from binary to decimal and the decimal taps connected together in groups of two, three, four, five, etc. to produce multiple or weighted outputs from the decoder. These outputs are then applied to a bit change which produces an output whenever it receives an input.
A further dissertation on weighted random pattern testing can be found in an article by H. D. Schnurmann et al. entitled "The Weighted IRandom Test-Pattern Generator", IEEE Transactions on Computers, Vol. C-24, No. 7, July 1975 at page 695 et seq.
Yet another expedient to improve testability is to build into the chip additional circuit connections for the sole purpose of testing. Obviously these circuits must be kept to a minimum, consistent with testing needs, because they reduce the availability of circuits for the routine function of the device. A device, exemplifying this built-in testability, is described in the Eichelberger U.S. Pat. No. 3,783,254, assigned to the assignee of the instant application. In Eichelberger, a shift register portion of a level sensitive scan device (LSSD) can receive inputs directly from an external connection and deliver an output, and are thus directly accessible for testing.
The use of "signatures" in lieu of a comparison of every individual test response with a known good output response is taught by Gordon et al. in U.S. Pat. No. 3,976,864.
While the prior art testing methods were suitable for testing devices of the then-existing complexity, the increase in circuit density requires more sophisticated testing techniques, not only to reduce testing time, but to assure the functional integrity of these devices. While a defective integrated circuit cannot be repaired, it would be most useful if one were able to diagnose the failure mode of the device to at least a few fault-prone elements so that process changes in the manufacturing of the device could be instituted to minimize the number of faults.
BIST (Built In Self Test) design, WRP (Weighted Random Pattern), and deterministic pattern test methodologies have evolved mainly in support of LSSD logic and structural testing, which is today the prevailing main design and test approach. The STUMPS structure shown in FIG. 1 illustrates a typical testing system 10 and chip design that incorporates these test methodologies. This structure utilizes a Linear Feedback Shift Register (LFSR) 12 which applies test vectors to an integrated circuit device under test (DUT) 14. After each clock cycle, a different test vector is applied to DUT 14. The outputs of DUT 14 are inputted into a Multiple Input Shift Register (MISR) 16.
These test methodologies allow for three distinct test modes. The first mode is based on deterministic LSSD and test techniques as shown and described in U.S. Pat. No. 3,783,254. It is fully compatible with the original structural test modes used since the early development of LSSD. In this mode the tester supplies the patterns to be loaded in each SRL (Shift Register Latches) chain and then pulses the appropriate system clocks. The problem encountered with this approach is that the generation and storage (at the tester) of the deterministic patterns is relatively expensive.
To overcome this problem the WRP methodology was developed. This second test mode utilizes a Linear Feedback Shift Register (LFSR) to algorithmically generate a set of pseudo random test patterns at the tester as shown and described in U.S. Pat. Nos. 4,688,223, 4,745,355 and 4,801,870. These patterns are then biased or weighted to optimize them for a specific logic design. In addition, a Multiple Input Signature Register (MISR) is used to compress the DUT responses into a signature for eventual comparison to a predetermined good signature. Although this approach has advantages in test pattern volumes and generation cost, it requires special tester hardware.
The third test mode is based on extending some of these techniques to BIST and incorporates the LFSR and MISR in the DUT. The advantage of this approach is that it lessens the dependency on external test hardware support. The problem encountered here is that the patterns generated by the LFSR are "flat random" patterns that usually result in relatively low test coverage or excessive test time.
What is needed is a solution for testing dense VLSI chips which combines all three techniques or test modes described above to balance the three test modes so as to optimize test time, test data volume, and test coverage.